This invention relates to clock generators generally, and more particularly to a phase-locked-loop frequency synthesizer having post production configuration capabilities contained on an EPROM.
It is well. known to construct a clock generator that has a fixed frequency which is determined during the silicon wafer fabrication of the clock generator. The frequency of the clock generator is determined by using a specific pattern during the manufacturing process involved in the wafer production of the clock generator. An important competitive advantage can be obtained by providing a clock generator that can be configured late in the manufacturing process, preferably after wafer fabrication. Phase-locked-loop (PLL) based clock generators typically use read only memory (ROM) tables to store frequency selection and configuration information. This information can be altered by using a device specific mask during wafer fabrication. A disadvantage with this technique is that once the device has been fabricated, the device can no longer be reconfigured.
Another technique used to obtain late configuration for PLL-based clock generators is accomplished by implementing a number of electrically programmable fuses made of aluminum, polysilicon or some other type of material that is appropriate for fuse fabrication. These fuses could then be programmed after production of the clock generator. The fuse technique provides somewhat of a competitive advantage by reducing the number of parts required to be, stored in inventory at any given time. The late programming of the fuses also reduces the time necessary to produce the clock generator. However, this technique suffers from the disadvantage of having limited configuration information that can be stored. As a result, the implementation of new frequency clock generators would require mask programming during fabrication to realize the new frequencies. Some prior art devices do implement more than one frequency table on a single ROM, but are limited to the specific pre-defined frequencies available in the ROM mask. Furthermore, it is not possible to test the fuses without blowing them, which permanently alters the device.
Another technique which could be used to obtain late configurations for clock generators is accomplished by using laser configurable parts which can be programmed using a polysilicon or aluminum link similar to the fuse technique. Also similar to the fuse technique example would be the disadvantage of storing only a limited amount of configuration information. It does not appear that the prior art has proposed a solution to the problem of providing a clock generator that is programmable late in the manufacturing cycle, can store enough configuration information to be commercially practical and can be manufactured at an acceptable cost.
The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming functionality can be verified. All of these features are accomplished without the use of programming fuses.
Objects, features and advantages of the present invention are to provide a clock generator that uses an on-chip EPROM in a monolithic clock generator chip, can be adapted to various PLL-based clock generators, can be electrically configured, can be erased prior to packaging, reduces cycle time from customer requests to prototypes, and can be field programmed if desired.